49 research outputs found
Context Awareness for Self-adaptive and Highly Available Production Systems
Part 8: Robotics and ManufacturingInternational audienceA new approach for the realization of self-adaptive and highly available production systems based on a context aware approach, allowing self-adaptation of flexible manufacturing processes in production systems and effective knowledge sharing to support maintenance, is presented. The usage of dynamically changing context as basis for adaptation of flexible manufacturing lines/processes and effective knowledge sharing is proposed. The presented solution includes services for context extraction, adaptation and self-learning allowing high adaptation of production systems depending on the identified context. A generic architecture following Service Oriented Principles is presented allowing for integration of the proposed solution into various production systems. A successful initial application of the developed solution in real world manufacturing environment is presented
A DIN Spec 91345 RAMI 4.0 Compliant Data Pipelining Model: An Approach to Support Data Understanding and Data Acquisition in Smart Manufacturing Environments
Today, data scientists in the manufacturing domain are confronted with various communication standards, protocols and technologies to save and transfer various kinds of data. These circumstances makes it hard to understand, find, access and extract data needed for use case depended applications. One solution could be a data pipelining approach enforced by a semantic model which describes smart manufacturing assets itself and the access to their data along their life-cycle. Many research contributions in smart manufacturing already came out with with reference architectures like the RAMI 4.0 or standards for meta data description or asset classification. Our research builds upon these outcomes and introduces a semantic model based DIN Spec 91345 (RAMI 4.0) compliant data pipelining approach with the smart manufacturing domain as exemplary use case. This paper has a focus on the developed semantic model used to enable an easy data exploration, finding, access and extraction of data, compatible with various used communication standards, protocols and technologies used to save and transfer data.publishersversionpublishe
Dynamic Power Management for Neuromorphic Many-Core Systems
This work presents a dynamic power management architecture for neuromorphic
many core systems such as SpiNNaker. A fast dynamic voltage and frequency
scaling (DVFS) technique is presented which allows the processing elements (PE)
to change their supply voltage and clock frequency individually and
autonomously within less than 100 ns. This is employed by the neuromorphic
simulation software flow, which defines the performance level (PL) of the PE
based on the actual workload within each simulation cycle. A test chip in 28 nm
SLP CMOS technology has been implemented. It includes 4 PEs which can be scaled
from 0.7 V to 1.0 V with frequencies from 125 MHz to 500 MHz at three distinct
PLs. By measurement of three neuromorphic benchmarks it is shown that the total
PE power consumption can be reduced by 75%, with 80% baseline power reduction
and a 50% reduction of energy per neuron and synapse computation, all while
maintaining temporary peak system performance to achieve biological real-time
operation of the system. A numerical model of this power management model is
derived which allows DVFS architecture exploration for neuromorphics. The
proposed technique is to be used for the second generation SpiNNaker
neuromorphic many core system
A RISC-V MCU with adaptive reverse body bias and ultra-low-power retention mode in 22 nm FD-SOI
We present a low-power, energy efficient 32-bit RISC-V microprocessor unit
(MCU) in 22 nm FD-SOI. It achieves ultra-low leakage,even at high temperatures,
by using an adaptive reverse body biasing aware sign-off approach, a low-power
optimized physical implementation, and custom SRAM macros with retention mode.
We demonstrate the robustness of the chip with measurements over the full
industrial temperature range, from -40 {\deg}C to 125 {\deg}C. Our results
match the state of the art (SOTA) with 4.8 uW / MHz at 50 MHz in active mode
and surpass the SOTA in ultra-low-power retention mode.Comment: accepted at ISOCC 202
VLSI Implementation of a 2.8 Gevent/s Packet-Based AER Interface with Routing and Event Sorting Functionality
State-of-the-art large-scale neuromorphic systems require sophisticated spike event communication between units of the neural network. We present a high-speed communication infrastructure for a waferscale neuromorphic system, based on application-specific neuromorphic communication ICs in an field programmable gate arrays (FPGA)-maintained environment. The ICs implement configurable axonal delays, as required for certain types of dynamic processing or for emulating spike-based learning among distant cortical areas. Measurements are presented which show the efficacy of these delays in influencing behavior of neuromorphic benchmarks. The specialized, dedicated address-event-representation communication in most current systems requires separate, low-bandwidth configuration channels. In contrast, the configuration of the waferscale neuromorphic system is also handled by the digital packet-based pulse channel, which transmits configuration data at the full bandwidth otherwise used for pulse transmission. The overall so-called pulse communication subgroup (ICs and FPGA) delivers a factor 25–50 more event transmission rate than other current neuromorphic communication infrastructures
Neuromorphic Hardware In The Loop: Training a Deep Spiking Network on the BrainScaleS Wafer-Scale System
Emulating spiking neural networks on analog neuromorphic hardware offers
several advantages over simulating them on conventional computers, particularly
in terms of speed and energy consumption. However, this usually comes at the
cost of reduced control over the dynamics of the emulated networks. In this
paper, we demonstrate how iterative training of a hardware-emulated network can
compensate for anomalies induced by the analog substrate. We first convert a
deep neural network trained in software to a spiking network on the BrainScaleS
wafer-scale neuromorphic system, thereby enabling an acceleration factor of 10
000 compared to the biological time domain. This mapping is followed by the
in-the-loop training, where in each training step, the network activity is
first recorded in hardware and then used to compute the parameter updates in
software via backpropagation. An essential finding is that the parameter
updates do not have to be precise, but only need to approximately follow the
correct gradient, which simplifies the computation of updates. Using this
approach, after only several tens of iterations, the spiking network shows an
accuracy close to the ideal software-emulated prototype. The presented
techniques show that deep spiking networks emulated on analog neuromorphic
devices can attain good computational performance despite the inherent
variations of the analog substrate.Comment: 8 pages, 10 figures, submitted to IJCNN 201